The present invention relates generally to semiconductor devices and device fabrication and more particularly to non-planar semiconductor devices and device fabrication.
One of the challenges in scaling transistors to increasingly smaller geometries is controlling leakage current while increasing drive current. Fully depleted devices such as ETSOI, tri-gate, and finfet devices offer the promise of excellent control of short channel effects (e.g., barrier lowering, punch-through, surface scattering, velocity saturation, impact ionization, and hot electrons). However, fully depleted devices suffer from high extension region resistance that degrades device performance.
One of the factors in high extension region resistance is traditional ion implantation that is used to dope selected regions of semiconductor devices. The bombardment of ions during traditional ion implantation destroys much of the crystalline structure resulting in many non-crystalline (amorphous) regions. Unlike planar structures, which do not have surface discontinuities, the discontinuities of non-planar devices impede re-crystallization from intact crystalline regions (also known as seeds) during high temperature annealing. As a result, non-planar devices have higher resistivity than planar devices. Furthermore, traditional ion implantation leaves the extension region of a device (e.g., the area below the lateral spacers of the gate) undoped, resulting in even higher device resistance.